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Application Note 9822
Appendix B Schematic Diagrams
(Continued)
+5V D
+
1
CLK IN
J2
C51
0.1 μ F
C47
0.1 μ F
13
U5
AC04
C18 C42
4.7 μ F 0.1 μ F
U5
12
14
2
CLK1
R19
56.2
L1
1.5 μ H
U5
9
7
AC04
8
(CLK)
+5V D
+
VR2
1(CCW)
2
AC04
C49 C50
4.7 μ F 0.1 μ F
1.0K
3(CW)
R18
100
C46
0.1 μ F
U5
11
10
AC04
CLK3
(CLK)
U5
3
4
AC04
U5
5
6
AC04
CLK4
(CLK)
FIGURE 13. SAMPLE CLOCK DRIVER CIRCUIT
AGND
TEST
POINT
DGND
TEST
POINT
E9 E10
FB5
TP1
TP3
TP2
TP4
E1
E2
FB1
+5V AIN
+5V A
+5V DIN
+5V D
AGND
+
C53
4.7 μ F
C52
0.1 μ F
(ANALOG INPUT AND REFERENCE
DGND
+
C20 C19
4.7 μ F 0.1 μ F
(SAMPLE CLOCK
GENERATOR)
VOLTAGE GENERATOR OP-AMPS,
BANDGAP REFERENCE)
E11 E12
E5
E6
+5V A1IN
AGND
+
FB6
C55 C54
4.7 μ F 0.1 μ F
+5V A1 (A/D AV CC )
+5V D1IN
DGND
+
FB3
C24 C23
4.7 μ F 0.1 μ F
+5V D1
(A/D DV CC1 )
AGND AND DGND TIE TOGETHER
AT A SINGLE POINT WHERE
THE POWER SUPPLIES
C21
-5V AIN
AGND
E7
E8
+
C45
4.7 μ F
FB4
C48
0.1 μ F
ENTER THE PWB
-5V A
(ANALOG INPUT AND REFERENCE
VOLTAGE GENERATOR OP-AMPS,
+5V D2IN
DGND
E3
E4
+
FB2
C22
4.7 μ F 0.1 μ F
+5V D2
(+5V/+3V)
(A/D DV CC2 )
BANDGAP REFERENCE)
FIGURE 14. ANALOG AND DIGITAL POWER SUPPLIES
3-10
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